FPGA related projects...

This are projects I use within the arcade FPGA activities, but it is worth to mention and publish them including the source code separately. Most of them I use for my arcade & computing projects.

EjLA - Embedded jTAG Logic Analyzer:

A Xilinx Chipscope replacement!

I am using Xilinx FPGAs a lot. I don't use them commercially and for a hobby I can't (do not want to) invest (so much) in buying support tools where I "spent already enough" to get and use the products (like jTAG interface, evaluation boards and a lot of time and own board setups to get used to its specifics). Basically I am also doing quite some dissemination work for the products as well on my project web pages, I'd say!
Ok, without paying, it is not possible to use some features which are not free - like Chipscope.

Having a logic analyzer for digital design verification is a must, so I spent the money in an stand-alone tool instead of something only working within Xilinx FPGA fabrics - so I can also use it with an Altera or Actel board :-)

But for some of my projects, like the FPGA-DIL replacement board which has quite limited I/O, having some tools providing better obervability would be still more than a "nice to have".
So I thought about having a useful replacement for Chipscope, without wasting may pins and FPGA resources.

I checked out how to use the jTAG interface on Xilinx products. There was not really a lot of documentation around, so I did (and had to do) my own investigations. Finally I was able to set up some basic FPGA code, forming a basic logic analyzer core. I did a complete new setup, as the code I saw on the web was not really resource-saving (these solutions intend to form a stand alone LA, not a lean add-on to other FPGA code...).

Features:
- uses the conventional jTag port of the Xilinx device
- uses only a clock, trigger and 32 input channels
- it has a simple length-encoding, thus it can sample up to ~8k x 32 channel samples with one BRAM block
(minimum always captured is ~0,5k x 32 channels), more BRAM blocks are possible as well
- works at least up to 100MHz clock speed on a Spartan 3e
- supports one mask/value trigger (32 channels)
- supports selectable pre/post trigger capturing
- supports a sample clock divider
- will support trigger delay (not yet included)
- will support selectable int/ext trigger (currently int and ext is ORed)
- does not require any Xilinx license, just a basic Web ISE setup
- Low utilization: ~11% LUTs, ~11% Slice-FF, 22% Slices, 3 GCLK, 1 BRAM of a xc3s100e!

Beside the FPGA stuff, having some smart solution on the PC side is of similar importance.
I did not want to spend too much time and effort in any fancy GUI, so I selected the client of SUMP's logic analyzer (see my links page you can find on the navigator bar on the left).
It is just what I required: a simple GUI for parameter setup and a waveform viewer. Furthermore (which I consider even more important) it does not require a degree in rocket science and a specially configured development operating system plus tons of libraries to get the code compiled - just the JAVA JDK and the classic Eclipse installation was sufficient.
The only missing link was the jTAG configuration. Again, there is a lot available out there. After some tries with different USB projects and half a day work to get my PC cleaned up again with these self-made USB drivers, I decided not to use any of them.
I decided to use the impact tool delivered with the ISE setup. I just had to set up a small wrapper I called the "EJLA_server" to translate my commands to the impact tool and decode the returned data. This also keeps the SUMP JAVA code simple and robust and it should automatically work with any jTAG cable the Xilinx impact tool supports!
Basically it opens also the use of any other client GUI, it just needs to connect to the ejla_server binary. If you are developing such GUIs and interested in adding this LA to your supported clients, drop me a mail with a certain comment using the code request link below!

Click here to proceed to the code request page.
Please note that especially for this work I expect some nice, friendly mail - not only a "send the code" message. The EjLA core is NOT to be used for commercial purposes, only for hobbyists (we can talk about this, though)!


µCore8 - an ultra small, FPGA-suited controller core:

I use this core to do miscellaneous control stuff on my own arcade replay board implementation.

Features:

It can be programmed with a simple assembler under Win32 (modified from the picoasm project I got from MikeJ).

I can provide a basic Xilinx project including the VHDL code, some example assembly code, the assembler source code itself and a opcode overview page as PDF.
I use it for my replay projects.

Click here to proceed to the code request page

i2c_master_peri - a lean i2c master peripheral:

This peripheral block is used together with the µCore8 to initialize i2c devices on my arcade replay board.

Features:

I can provide a basic Xilinx project including the VHDL code.
I use it for my replay projects.

Click here to proceed to the code request page

uart_peri - a lean uart peripheral:

This peripheral block is used together with the µCore8 for debugging I/O on my arcade replay board.

Features:

I can provide a basic Xilinx project including the VHDL code.
I use it for my replay projects.

Click here to proceed to the code request page